This invention relates generally to techniques for packaging and interconnecting integrated circuits and, more particularly, to techniques for packaging and interconnecting integrated circuits covering an entire semiconductor wafer.
Integrated circuits are generally fabricated on a wafer of semiconductor material, such as silicon, and cut into individual integrated-circuit (IC) chips. Each IC chip is then encapsulated in a chip package, typically of plastic or ceramic, to protect the chip from contamination and provide input/output pins for soldering the chip onto a printed circuit board. Inside the chip package, the input/output contact areas of the IC chip are electrically connected to the input/output pins of the chip package by soldering extremely fine wires between the chip contact areas and the package pins.
Although this type of IC chip packaging construction is widely used, it has several disadvantages, especially when used in more advanced circuit applications. One disadvantage is that the chip packages require a large volume, thus severely limiting the chip densities that can be achieved. Another disadvantage is that the resulting long interconnection lengths between IC chips contribute to signal propagation delays and signal distortions. Still another disadvantage is that the use of fine soldered wires between the chip contact areas and the package pins requires expensive tooling and special labor, causes poor quality connections and increases the inductance of the interconnections.
To minimize these disadvantages, integrated circuits covering an entire semiconductor wafer have been fabricated. These wafer scale integrated circuits reduce the distances between circuits, thus providing faster switching speeds, while reducing the number of interconnections between circuits, thus lessening the probability of defective interconnections. In addition, the volume required by a wafer scale integrated circuit is substantially less than the volume required by the same integrated circuit on multiple IC chips.
Several different packaging constructions for semiconductor wafers are disclosed in U.S. Pat. No. 4,603,374 to Wasielewski, U.S. Pat. No. 4,755,910 to Val and U.S. Pat. No. 4,484,215 to Pappas. However, all of these packaging constructions rely on the conventional interconnection techniques discussed above and do not attempt to minimize the lead lengths between interconnected circuits or provide a high packing density. The present invention is directed to these ends.